1. Field of the Invention
The present invention relates to a semiconductor device having improved contact characteristics between a semiconductor layer and a metal electrode.
2. Description of the Related Art
A high-density, high-performance MOS integrated circuit formed on an Si substrate is conventionally attained by micropatterning elements. More specifically, it is very important to decrease the gate length of a field effect transistor (FET) in order to not only decrease the element area but also improve the current driving force and the operation speed of the element. In this case, although the junction depth of a diffusion layer must be decreased to prevent a short-channel effect, a decrease in thickness of the diffusion layer is limited.
The ON-resistance of a MOSFET is determined by not only the channel resistance but also a sum of parasitic resistances such as the diffusion layer resistance of a source-drain region and the contact resistance between a metal and the source-drain region. Therefore, even when the junction depth of the diffusion layer is maximally decreased, when the channel resistance becomes equal to the parasitic resistance by micropatterning, a further increase in driving force cannot be expected, and the operation speed is not improved.
In a conventional FET, the thickness of a diffusion layer of a source-drain region is decreased. However, even when the thickness of the diffusion layer is maximally decreased, there is a large contact resistance between the source-drain region and a metal electrode. For this reason, an increase in driving force of the FET cannot be expected, and the operation speed cannot increased.